1. Field of the Invention
The present invention relates to an audio processor for use in reproducing audio data transmitted through a digital interface such as an IEEE1394 interface or a high-definition multimedia interface (HDMI) for DVD players, digital television sets and AV amplifiers, for example.
2. Description of the Related Art
With a digital interface such as an IEEE1394 interface or an HDMI, it is possible to select a rate (frequency) from a plurality of sampling rates to transmit audio data.
In an audio processor for use in reproducing audio data transmitted through a digital interface as described above, to reproduce audio data, an audio clock signal having the same frequency as the sampling rate of transmitted audio data is generated using a phase locked loop (PLL) circuit in many cases (see, for example, Japanese Unexamined Patent Publication No. 2004-248123).
In this PLL circuit, feedback control is performed such that a comparison clock signal obtained by dividing the frequency of an audio clock signal by a given frequency division ratio is synchronized with a reference clock signal having a frequency which is allowed to be used at a receiver, thereby generating an audio clock signal obtained by performing frequency multiplication or division on the reference clock signal.
A PLL circuit as described above is configured to change the frequency division ratio using, for example, a noise shaver and is capable of dealing with a plurality of sampling rates (see, for example, Japanese Unexamined Patent Publication No. 11-341306). In this case, the frequency division ratio needs to be previously determined. In the case of a digital interface in the HDMI, for example, this frequency division ratio is considered to be determined by obtaining a sampling frequency FS from an equation: 128×FS=(CTS×Pixel Clock)/N, using N information and CTS included in a packet called clock regeneration packet (CRP) when audio data is transmitted.
However, the determination of a frequency division ratio using such an equation tends to cause the problem of increase in circuit scale of an audio processor in a configuration in which a section for determining the frequency division ratio is formed by hardware. In addition, operation time is needed, so that there arises another problem in which the lock time of audio data increases.